1) Field of the Invention
This invention relates to a method of manufacturing semiconductor devices comprising a metal layer.
2) Description of the Prior Art
In semiconductor integrate circuit manufacturing, metals are formed into patterned layers to make electrical connections to and between individual devices on a silicon substrate, such as sources, drains, and gates of field effect transistors (FET's). Metal maybe deposited over the substrate, dielectric layers and other structures, such as gate structures. In the simplest method, a free surface is blanketed with metal and the deposited metal is then patterned to form the desired interconnection configuration. In the current semiconductor process, aluminum is the most widely used material; but other refractory materials are being used, tungsten in particular. Blanket layers of metal can be deposited by low pressure chemical vapor deposition (LPCVD) and the patterning of metal layers can be accomplished by conventional lithographic and etching (plasma or sputter) etching techniques.
To form more accurate contacts between buried devices in the substrate, such as source and drain impurity regions, a method of forming self aligned contacts (SAC) is often used. A self aligned contact is formed by patterning layers or structures around a contact area so that when a metal layer is formed over the structures and the contact region, the metal forms an electrical connection with the impurity regions in the substrate, e.g. a source or drain region. However, self aligned contacts often suffer from several problems, such as poor metal contact with the substrate because of poor "step coverage" over the underlying structures, e.g., over oxide sidewall spacers. Also, when metal is formed directly on the substrate surface, the metal consumes a portion of the substrate causing the underlying source or drain junction to be formed deeper in the substrate.
A conventional process for forming a self aligned contact with a metal layer is shown in FIGS. 1 through 4. As shown in FIG. 1, gate structures 28, 30 are formed on a semiconductor substrate 10 using conventional processes which are commonly known to those skilled in the art. Therefore only the elements will be described, not the processes. The gate structures 28, 30 are comprised of: gate oxide layer 16, gate 18, top oxide layer 20 (also referred to as self aligned contact oxide layer), oxide sidewalls spacers 24. The substrate 10 has two silicon substrate diffusions, a N- diffusion (referred to as a lightly doped source or drain) 12 and a N+ diffusion (referred to as a heavily doped source or drain) 14.
Referring to FIG. 2, a inter-poly oxide layer 32 is formed on the device surface. The term "device surface" is used herein to include all layers and structures formed on the substrate. Next, portions of the inter-poly oxide layer 32 between the gate structures 28, 30 are etched (called a self-aligned contact etch) to expose the oxide sidewalls 24 and the contact area 26 as illustrated in FIG. 3.
Subsequently, a polysilicon layer 34 is formed with a thickness in the range of 500 to 600 .ANG. on the device surface as illustrated in FIG. 4. The polysilicon layer 34 then implanted with impurity ions to increase its conductivity. Polysilicon layer 34 is deposited between the metal layer 36 and the oxide layers 24, 32 to prevent the pealing of the metal layer 36 from the device surface. A metal layer 36, preferably tungsten silicide, is formed over the polysilicon layer 34. The tungsten silicide layer 36 forms an electrical connection with the substrate and the underlying source/drain region 12, 14 in the contact area 26. This process is self aligning since the tungsten silicide connections/contacts 26 to the source/drain diffusion 12 14 are defined using the oxide sidewall spacers 24 as the mask. This self aligning contact process eliminates less precise and more costly lithography process steps.
However, the conventional self align contact process has several drawbacks. First, the source/drain junctions are driven deeper into the substrate because additional impurity ions from the heavily doped N+ polysilicon layer are driven into the source/drain regions during subsequent heat processing, such as the contact flow process at about 900 C.degree.. The deeper source/drain junction depth can induce a large leakage current and device punchthrough.
In addition, with the conventional process, the contact resistance will increase in small contact areas because the step coverage of the metal 36 (tungsten silicide) is poor. The thickness of inter-poly silicon takes up surface area which could be used to form metal contact areas thus the inter-poly layer effectively decreases the contact opening area. Also, tungsten silicide is difficult to deposit within small contact areas and to establish an electrical connection between the silicide and the source/drain.
U.S. Pat. No. 4,985,371 to Rana et al., teaches a method to produce thick highly conductive metal layers having small grain sizes so that the grain size will not prevent the metal layer from being formed into accurate small patterns. The method comprises forming a series of alternating layers of metal and "metal grain-growth interrupting material." Where tungsten is the metal, silicon is the preferred grain-growth interrupting material.
U.S. Pat. No. 4,904,620 to Schmitz teaches a method of forming titanium disilicide layers where a series of alternating layers of titanium and silicon are deposited on a substrate. The layers are heat treated to form a titanium disilicide layer.